1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a process for fabricating a semiconductor device including an improved phosphorous-doped silicon dioxide dielectric layer.
2. Description of the Related Art
Microelectronic integrated circuit chips typically include a number of semiconductor and metal interconnect layers which must be electrically insulated from each other by dielectric layers. The surfaces of such chips are also typically encapsulated by protective dielectric passivation layers.
Tetraethylorthosilicate (TEOS) is a material which can be advantageously reacted with oxygen to form a silicon dioxide (SiO.sub.2) dielectric layer for these purposes. TEOS can be used to form silicon dioxide layers using Plasma Enhanced Chemical Vapor Deposition (PECVD) technique at a relatively low temperature on the order of 400.degree. C.
Silicon dioxide films formed from TEOS provide excellent step coverage, and undoped silicon dioxide films, also known as undoped silicon glass (USG) films, are used as poly-metal interlevel dielectric (PMD) materials in some integrated circuit fabrication processes. However, films formed of this material are disadvantageous in that they have relatively low polish rates and selectivity. This latter characteristic refers to the difference in etch rates between the silicon dioxide glass and an underlying silicon oxynitride etch stop layer as will be described in detail below. It is desirable for the silicon dioxide layer to etch much faster than the silicon oxynitride layer.
In addition, undoped silicon dioxide films cannot be reflowed as required by a number of processes. In order to add the reflow capability to these films, the material must be doped with phosphorous or boron. Phosphorous-doped silicon dioxide is also known as phosphorous-doped silicon glass (PSG). Phosphorous doping also produces a number of beneficial effects, including increased selectivity and a high polish rate which increases process throughput. Phosphorous doping also enhances gettering (the ability of crystalline defects to capture harmful impurities).
An exemplary semiconductor process which uses silicon dioxide glass is known in the art as "tungsten damascene". This process produces local interconnects which can be advantageously applied to semiconductor devices such as flash Electrically-Erasable Programmable Read-Only Memories (EEPROMs). The process includes forming an insulator layer of silicon dioxide glass over the memory cells, and then planarizing the insulator layer using chemical-mechanical polishing. Reactive Ion Etching (RIE) is then performed to form vertical interconnect holes through the glass down to interconnect areas (source, drain, etc.) of the cells. The holes are filled with tungsten which ohmically contacts the interconnect areas to form the local interconnects.
The silicon dioxide etch is conventionally performed using octafluorobutene (C.sub.4 F.sub.8) etchant, which also has a high etch rate for silicon. For this reason, a mechanism must be provided for performing the silicon dioxide etch without allowing the etchant to act on the silicon of the underlying interconnect areas.
Such a mechanism includes forming a silicon oxynitride etch stop layer underneath the silicon dioxide layer, and performing the etch in two stages. The first stage is the octafluorobutene etch through the silicon dioxide layer, which terminates at the etch stop layer since octafluorobutene has a low etch rate for silicon oxynitride (selectivity as discussed above). Then, a second RIE etch is performed using fluoromethane (CH.sub.3 F), which forms holes through the portions of the etch stop layer that are exposed through the holes in the silicon dioxide layer, down to the interconnect areas of the devices. This is possible because fluoromethane has a high etch rate for silicon oxynitride, but a low etch rate for silicon dioxide.
The structure can be further facilitated by using a silicide technique to increase the conductivity of the interconnect areas of the cells. Siliciding is a fabrication technique that enables electrical interconnections to be made that have reduced resistance and capacitance.
The silicide process comprises forming a layer of a refractory metal silicide material such as tungsten, titanium, tantalum, molybdenum, etc. on a silicon interconnect area (source or drain diffusion region) or on a polysilicon gate to which ohmic contact is to be made, and then reacting the silicide material with the underlaying silicon material to form a silicide surface layer having much lower resistance than heavily doped silicon or polysilicon. A silicide surface layer formed on a polysilicon gate is called "polycide", whereas a silicide surface layer formed on silicon using a self-aligned process is called "salicide".
Phosphorous doping of TEOS based silicon dioxide dielectric layers or films is conventionally performed by the addition of trimethylphosphite (TMP). However, TMP is a liquid and must be vaporized in order to form a dielectric layer using PECVD. This additional step is not compatible with some PECVD deposition chambers. In addition, the vaporization step results in low uniformity and poor process control.
Another conventional dielectric material is formed by the deposition of silane (SiH.sub.4) and phosphine (PH.sub.3). However, this material is disadvantageous in that it provides poor step coverage.